xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../Xilinx/Vivado/2017.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../Xilinx/Vivado/2017.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../Xilinx/Vivado/2017.1/data/ip/xpm/xpm_VCOMP.vhd,
blk_mem_gen_v8_3.v,verilog,blk_mem_gen_v8_3_6,../../../ipstatic/simulation/blk_mem_gen_v8_3.v,
code_rom.v,verilog,xil_defaultlib,../../../../lab1_comp_verilog.srcs/sources_1/ip/code_rom/sim/code_rom.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
