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-- Company:
-- Engineer:
-- 
-- Create Date:    14:04:07 05/16/2014 
-- Design Name: 
-- Module Name:    bunshu - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bunshu is
  port (
    CLK : in std_logic;
    RST : in std_logic;
    CEOUT : out std_logic
  );
end bunshu;

architecture Behavioral of bunshu is

--signal Q : std_logic_vector(2 downto 0); --sim
signal Q : std_logic_vector(23 downto 0); --board

begin

process (CLK) begin
  if CLK='1' and CLK'event then
    if RST='1' then 
      Q <= (others => '0');
    elsif ( Q = 9999999) then
      Q <= (others => '0');
    else
      Q <= Q + 1;
    end if;
  end if;
end process; 

process (Q) begin
--if Q = "111" then --sim
  if ( Q = 9999999) then --board
    CEOUT <= '1';
  else
    CEOUT <= '0';
  end if;
end process;

end Behavioral;

