# 
# Synthesis run script generated by Vivado
# 

set_msg_config -id {Common 17-41} -limit 10000000
create_project -in_memory -part xc7a100tcsg324-1

set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.cache/wt [current_project]
set_property parent.project_path C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.xpr [current_project]
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
add_files C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/imports/ROM_COE/uart_code.coe
read_verilog -library xil_defaultlib {
  C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/imports/Verilog/RGB_controller.v
  C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/imports/Verilog/UART_TX.v
  C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/imports/Verilog/UART_TX_CTRL.v
  C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/imports/Verilog/Uart_TX_State.v
  C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/imports/Verilog/bunshu.v
  C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/imports/Verilog/counter.v
  C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/imports/Verilog/counter_top.v
  C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/imports/Verilog/led_ctl.v
  C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/imports/Verilog/meta_harden.v
  C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/imports/Verilog/seg7_out.v
  C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/imports/Verilog/uart_RX_count.v
  C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/imports/Verilog/uart_baud_gen.v
  C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/imports/Verilog/uart_rx.v
  C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/imports/Verilog/uart_rx_ctl.v
  C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/imports/Verilog/NEXYS_TOP.v
}
read_ip -quiet C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/PLL_Block/PLL_Block.xci
set_property used_in_implementation false [get_files -all c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/PLL_Block/PLL_Block_board.xdc]
set_property used_in_implementation false [get_files -all c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/PLL_Block/PLL_Block.xdc]
set_property used_in_implementation false [get_files -all c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/PLL_Block/PLL_Block_ooc.xdc]
set_property is_locked true [get_files C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/PLL_Block/PLL_Block.xci]

read_ip -quiet c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom.xci
set_property used_in_implementation false [get_files -all c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom_ooc.xdc]
set_property is_locked true [get_files c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom.xci]

# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
  set_property used_in_implementation false $dcp
}
read_xdc C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/constrs_1/imports/XDC/NEXYS_PIN_LOC.xdc
set_property used_in_implementation false [get_files C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/constrs_1/imports/XDC/NEXYS_PIN_LOC.xdc]

read_xdc C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/constrs_1/imports/XDC/NEXYS_Timing.xdc
set_property used_in_implementation false [get_files C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/constrs_1/imports/XDC/NEXYS_Timing.xdc]


synth_design -top NEXYS_TOP -part xc7a100tcsg324-1


write_checkpoint -force -noxdef NEXYS_TOP.dcp

catch { report_utilization -file NEXYS_TOP_utilization_synth.rpt -pb NEXYS_TOP_utilization_synth.pb }
