//----------------------------------------------------------------------------------
// Company:        hdLab
// Engineer:       K.Date
// 
// Create Date:    06/15/2015 
// Design Name:    NEXYS4_verilog
// Module Name:    NEXYS4_TOP 
// Project Name:   NEXYS4
// Target Devices: Artix-7
// Tool versions:  Vivado2014.3
// Description: 
//
// Dependencies: 
//
// Revision: 1.00
// Revision 1.00 - File converted to verilog
// Additional Comments: 
//
//--------------------------------------------------------------------------------
//
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//              uninterrupted or error free, or that defects in the Designs
//              will be corrected. Furthermore, Xilinx does not warrant or
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//  Copyright © 2002, 2008 Xilinx, Inc.
//  All rights reserved
//
//----------------------------------------------------------------------------------

module uart_RX_count #(
    parameter CLOCK_RATE = 100000000,                                      // clock rate
    parameter BAUD_RATE  = 115200                                          // desired baud rate
    )  (
	input			clk,
	input			reset,
	input			rxd,
	output	[4:0]	DOUT1,
	output	[4:0]	DOUT2,
	output	[4:0]	DOUT3,
	output	[4:0]	DOUT4
	);

	// clock and controls
	wire			rst_clk_rx;
(* keep = "true" *)	wire			rx_data_rdy;
(* keep = "true" *)	wire	[7:0]	rx_data;
    
//attribute keep : string; 
//attribute keep of rx_data_rdy: signal is "TRUE";
//attribute keep of rx_data: signal is "TRUE";

	//
	// define the buffers for the incoming data, clocks, and control
	//
    // instantiate a metastability hardener for the incoming reset

	meta_harden	meta_harden_rst_i0 (
		.rst_dst(1'b0),
		.clk_dst(clk),
		.signal_src(reset),
		.signal_dst(rst_clk_rx)
	);

	//
	// And the button to switch LSB and MSB

	uart_rx #(
           .CLOCK_RATE(CLOCK_RATE),
           .BAUD_RATE(BAUD_RATE)
        ) uart_rx_i0 (
		.rst_clk_rx(rst_clk_rx),
		.clk_rx(clk),
		.rxd_i(rxd),
		.rxd_clk_rx(),
		.rx_data(rx_data),
		.rx_data_rdy(rx_data_rdy),
		.frm_err()	// this signal not used in this design
	);

	// instantiate the LED controller
	led_ctl	led_ctl_i0 (
		.rst_clk_rx(rst_clk_rx),
		.clk(clk),
		.rx_data(rx_data),
		.rx_data_rdy(rx_data_rdy),
		.DOUT1(DOUT1),
		.DOUT2(DOUT2),
		.DOUT3(DOUT3),
		.DOUT4(DOUT4)
	);
endmodule
