//----------------------------------------------------------------------------------
// Company:        hdLab
// Engineer:       K.Date
// 
// Create Date:    06/15/2015 
// Design Name:    NEXYS4_verilog
// Module Name:    bunshu 
// Project Name:   NEXYS4
// Target Devices: Artix-7
// Tool versions:  Vivado2014.3
// Description: 
//
// Dependencies: 
//
// Revision: 1.00
// Revision 1.00 - File converted to verilog
// Additional Comments: 
//
//--------------------------------------------------------------------------------

module bunshu(
	input		   CLK,
	input          RST,
	output reg     CEOUT
	);

	reg 	[23:0]	Q;	//board

	always @(posedge CLK) begin
		if (RST == 1'b1) begin
			Q	<= 24'b0;
		end else if (Q == 24'd9999999) begin
			Q	<= 24'b0;
		end else begin
			Q	<= Q + 1;
		end
	end
	
	always @(Q) begin
		if (Q == 24'd9999999) begin	//board
			CEOUT	<= 1'b1;
		end else begin
			CEOUT	<= 1'b0;
		end
	end
	
endmodule
