--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   18:24:30 07/03/2014
-- Design Name:   
-- Module Name:   C:/training/NEXYS4/Uart_TX/UART_TX_TB.vhd
-- Project Name:  Uart_TX
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Uart_TX
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY UART_TX_TB IS
END UART_TX_TB;
 
ARCHITECTURE behavior OF UART_TX_TB IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Uart_TX
    PORT(
         RESET : IN  std_logic;
         CLK : IN  std_logic;
         UART_TXD : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal RESET : std_logic := '1';
   signal CLK : std_logic := '0';

 	--Outputs
   signal UART_TXD : std_logic;

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Uart_TX PORT MAP (
          RESET => RESET,
          CLK => CLK,
          UART_TXD => UART_TXD
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 
RESET <= '0' after 400 ns;


END;
