// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.1_AR69191 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017
// Date        : Wed Nov 29 01:52:49 2017
// Host        : Date-PC running 64-bit Service Pack 1  (build 7601)
// Command     : write_verilog -force -mode synth_stub
//               C:/training/Artix-7/NEXYS4/lab1_comp_VHDL/lab1_comp_VHDL.srcs/sources_1/ip/code_rom/code_rom_stub.v
// Design      : code_rom
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7a100tcsg324-1
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_6,Vivado 2017.1_AR69191" *)
module code_rom(clka, addra, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[5:0],douta[7:0]" */;
  input clka;
  input [5:0]addra;
  output [7:0]douta;
endmodule
