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-- Company: 
-- Engineer:
--
-- Create Date:   19:56:30 10/08/2014
-- Design Name:   
-- Module Name:   C:/training/NEXYS4/Buckup/Lab_ISE/uart_tx_rx_test.vhd
-- Project Name:  Lab1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: uart_led
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY uart_tx_rx_test IS
END uart_tx_rx_test;
 
ARCHITECTURE behavior OF uart_tx_rx_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT Uart_TX
    PORT(
         RESET : IN  std_logic;
         CLK : IN  std_logic;
         UART_TXD : OUT  std_logic
        );
    END COMPONENT;
    
    COMPONENT uart_RX_count
    PORT(
         clk : IN  std_logic;
         reset : IN  std_logic;
         rxd : IN  std_logic;
         DOUT1 : OUT  std_logic_vector(4 downto 0);
         DOUT2 : OUT  std_logic_vector(4 downto 0);
         DOUT3 : OUT  std_logic_vector(4 downto 0);
         DOUT4 : OUT  std_logic_vector(4 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';

 	--Outputs
   signal DOUT1 : std_logic_vector(4 downto 0);
   signal DOUT2 : std_logic_vector(4 downto 0);
   signal DOUT3 : std_logic_vector(4 downto 0);
   signal DOUT4 : std_logic_vector(4 downto 0);
   signal  RXD  : std_logic;
   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
 
   U1: Uart_TX PORT MAP (
          RESET => reset,
          CLK => clk,
          UART_TXD => RXD
        );
        
  U3 : uart_RX_count PORT MAP (
          clk => clk,
          reset => reset,
          rxd => RXD,
          DOUT1 => DOUT1,
          DOUT2 => DOUT2,
          DOUT3 => DOUT3,
          DOUT4 => DOUT4
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 
RESET <= '0' after 400 ns;



END;
