# 
# Synthesis run script generated by Vivado
# 

set_msg_config -id {Common 17-41} -limit 10000000
set_param project.vivado.isBlockSynthRun true
set_msg_config -msgmgr_mode ooc_run
create_project -in_memory -part xc7a100tcsg324-1

set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.cache/wt [current_project]
set_property parent.project_path C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.xpr [current_project]
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_ip -quiet c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom.xci
set_property used_in_implementation false [get_files -all c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom_ooc.xdc]
set_property is_locked true [get_files c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom.xci]

# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
  set_property used_in_implementation false $dcp
}
read_xdc dont_touch.xdc
set_property used_in_implementation false [get_files dont_touch.xdc]

set cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.runs/code_rom_synth_1 -new_name code_rom -ip [get_ips code_rom]]

if { $cached_ip eq {} } {

synth_design -top code_rom -part xc7a100tcsg324-1 -mode out_of_context

#---------------------------------------------------------
# Generate Checkpoint/Stub/Simulation Files For IP Cache
#---------------------------------------------------------
catch {
 write_checkpoint -force -noxdef -rename_prefix code_rom_ code_rom.dcp

 set ipCachedFiles {}
 write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ code_rom_stub.v
 lappend ipCachedFiles code_rom_stub.v

 write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ code_rom_stub.vhdl
 lappend ipCachedFiles code_rom_stub.vhdl

 write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ code_rom_sim_netlist.v
 lappend ipCachedFiles code_rom_sim_netlist.v

 write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ code_rom_sim_netlist.vhdl
 lappend ipCachedFiles code_rom_sim_netlist.vhdl

 config_ip_cache -add -dcp code_rom.dcp -move_files $ipCachedFiles -use_project_ipc -ip [get_ips code_rom]
}

rename_ref -prefix_all code_rom_

write_checkpoint -force -noxdef code_rom.dcp

catch { report_utilization -file code_rom_utilization_synth.rpt -pb code_rom_utilization_synth.pb }

if { [catch {
  file copy -force C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.runs/code_rom_synth_1/code_rom.dcp c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom.dcp
} _RESULT ] } { 
  send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
  error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}

if { [catch {
  write_verilog -force -mode synth_stub c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom_stub.v
} _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}

if { [catch {
  write_vhdl -force -mode synth_stub c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom_stub.vhdl
} _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}

if { [catch {
  write_verilog -force -mode funcsim c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom_sim_netlist.v
} _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}

if { [catch {
  write_vhdl -force -mode funcsim c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom_sim_netlist.vhdl
} _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}


} else {


if { [catch {
  file copy -force C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.runs/code_rom_synth_1/code_rom.dcp c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom.dcp
} _RESULT ] } { 
  send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
  error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}

if { [catch {
  file rename -force C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.runs/code_rom_synth_1/code_rom_stub.v c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom_stub.v
} _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}

if { [catch {
  file rename -force C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.runs/code_rom_synth_1/code_rom_stub.vhdl c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom_stub.vhdl
} _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}

if { [catch {
  file rename -force C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.runs/code_rom_synth_1/code_rom_sim_netlist.v c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom_sim_netlist.v
} _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}

if { [catch {
  file rename -force C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.runs/code_rom_synth_1/code_rom_sim_netlist.vhdl c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom_sim_netlist.vhdl
} _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}

}; # end if cached_ip 

if {[file isdir C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.ip_user_files/ip/code_rom]} {
  catch { 
    file copy -force c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom_stub.v C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.ip_user_files/ip/code_rom
  }
}

if {[file isdir C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.ip_user_files/ip/code_rom]} {
  catch { 
    file copy -force c:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.srcs/sources_1/ip/code_rom/code_rom_stub.vhdl C:/training/Artix-7/NEXYS4/lab1_comp_verilog/lab1_comp_verilog.ip_user_files/ip/code_rom
  }
}
